This invention relates to the field of digital electronic memory devices, and in particular to a built-in apparatus and method for enhancing reliability by monitoring repair solution consistency.
Since users generally depend upon the reliability of integrated circuit chips for their own systems to function properly, it is common practice for the chip manufacturers to test the functionality of chips at the manufacturing site before the chips are sold to users. As the line width within a integrated circuit chip continues to shrink, this reliability becomes more difficult to achieve. An ongoing challenge for the manufacturers is to increase circuit density without sacrificing reliability or suffering decreasing chip yields due to malfunctioning parts.
Thus, before memory chips are released for shipment they typically undergo testing to verify that the support circuitry for the memory array and the individual circuitry for each of the memory cells within the memory array is functioning properly. One standard way for testing chip memories involves using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. An external memory tester supplies power and applies test patterns to the chip to detect faults. External memory testers can only test a limited number of chips at a time, and the test speed is limited by the external bus speed. Consequently, this method of testing is expensive in terms of time requirements and equipment costs.
Partly to address these issues, and partly to provide off-site testing, built-in self-test (BIST) units are now commonly incorporated into memory chips. Automated test equipment can now be simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the memory chip, and to monitor a single output signal from the chip. The on-board BIST unit generates all the test patterns and asserts (or de-asserts) the output signal if the chip passes the functionality test. The BIST can be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
The BIST unit operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a BIST unit writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the BIST unit is able to determine whether the memory cell is faulty. If too many errors are detected, then the fault may exist in the support circuitry.
It is not uncommon for a significant percentage of the memory cells within the chip to fail because of defects in the substrate or errors in the manufacturing process. To compensate for this, many memory chips are provided with a set of extra memory cells that can be used in place of the defective ones. Configuring the memory chip to replace the defective cells is termed xe2x80x9cRepairingxe2x80x9d the memory array. Some memory repair is performed at the manufacturing site. Conventional repairing techniques bypass the defective cells using fuseable links that cause address redirection. However, these techniques require significant capital investment for implementing the repairing process, and moreover fail to address the possibility of failure after shipment from the manufacturing facility.
To reduce repair costs and allow field repairs, some memory chips have been equipped with built-in self test (BIST) and built-in self repair (BISR) circuitry. The BIST circuit detects faults in the memory array and notifies the BISR circuit of the fault locations. The BISR circuitry generally reassigns the row or column containing the failing cell to a spare row or column in the memory array. BIST and BISR are typically performed each time power is applied to the system. This allows any latent failures that occur between subsequent system power-ups to be detected in the field.
Occasionally, the faults that occur in a memory chip are condition-sensitive. For example, some faulty cells may operate normally at power-up, but cease functioning under normal operating conditions. Other faults may be sensitive to the power supply voltage level. While BIST and BISR circuitry can compensate for these problems, changes in fault patterns of a chip are undesirable and may be symptomatic of underlying manufacturing problems. Consequently, it is desirable to provide a method of screening chips at the factory to detect fault pattern changes.
Accordingly, there is disclosed herein a memory device configured to detect changes in fault patterns. In one embodiment, the memory device includes a memory array, a built-in selftest (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address. During a verification phase, the BISR unit compares intercepted addresses designated by assertions of the error signal to the addresses previously stored in the training phase. If the faulty intercepted address fails to match a stored address, the BISR unit asserts a xe2x80x9cnew errorxe2x80x9d signal. If at the end of the verification phase, a stored address has not matched any intercepted faulty address, the BISR asserts a xe2x80x9cmissed errorxe2x80x9d signal.